mmMPCC2_MPCC_CONTROL_BASE_IDX 5432 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2
mmMPCC2_MPCC_CONTROL_BASE_IDX 6611 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2
mmMPCC2_MPCC_CONTROL_BASE_IDX 5673 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2