mmMPCC1_MPCC_TOP_SEL 5393 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC1_MPCC_TOP_SEL                                                                           0x164b
mmMPCC1_MPCC_TOP_SEL 6570 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_TOP_SEL                                                                           0x128c
mmMPCC1_MPCC_TOP_SEL 5632 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_TOP_SEL                                                                           0x128c