mmMPCC1_MPCC_SM_CONTROL 5401 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x164f
mmMPCC1_MPCC_SM_CONTROL 6578 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x1290
mmMPCC1_MPCC_SM_CONTROL 5640 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x1290