mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 6595 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 5657 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2