mmMPCC1_MPCC_MEM_PWR_CTRL 6594 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x1298
mmMPCC1_MPCC_MEM_PWR_CTRL 5656 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x1298