mmMPCC1_MPCC_CONTROL 5399 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC1_MPCC_CONTROL                                                                           0x164e
mmMPCC1_MPCC_CONTROL 6576 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_CONTROL                                                                           0x128f
mmMPCC1_MPCC_CONTROL 5638 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_CONTROL                                                                           0x128f