mmMPCC1_MPCC_BOT_SEL 5395 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC1_MPCC_BOT_SEL                                                                           0x164c
mmMPCC1_MPCC_BOT_SEL 6572 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC1_MPCC_BOT_SEL                                                                           0x128d
mmMPCC1_MPCC_BOT_SEL 5634 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC1_MPCC_BOT_SEL                                                                           0x128d