mmMPCC0_MPCC_TOP_SEL 5361 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_TOP_SEL                                                                           0x1630
mmMPCC0_MPCC_TOP_SEL 6536 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_TOP_SEL                                                                           0x1271
mmMPCC0_MPCC_TOP_SEL 5598 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_TOP_SEL                                                                           0x1271