mmMPCC0_MPCC_STATUS_BASE_IDX 5388 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2
mmMPCC0_MPCC_STATUS_BASE_IDX 6565 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2
mmMPCC0_MPCC_STATUS_BASE_IDX 5627 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2