mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 5386 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2
mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 6563 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2
mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 5625 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2