mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 5370 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2
mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 6545 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2
mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 5607 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2