mmMPCC0_MPCC_SM_CONTROL 5369 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1634
mmMPCC0_MPCC_SM_CONTROL 6544 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1275
mmMPCC0_MPCC_SM_CONTROL 5606 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1275