mmMPCC0_MPCC_OPP_ID 5365 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_OPP_ID                                                                            0x1632
mmMPCC0_MPCC_OPP_ID 6540 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_OPP_ID                                                                            0x1273
mmMPCC0_MPCC_OPP_ID 5602 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_OPP_ID                                                                            0x1273