mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 6561 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 5623 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2