mmMPCC0_MPCC_CONTROL_BASE_IDX 5368 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2
mmMPCC0_MPCC_CONTROL_BASE_IDX 6543 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2
mmMPCC0_MPCC_CONTROL_BASE_IDX 5605 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2