mmMPCC0_MPCC_CONTROL 5367 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC0_MPCC_CONTROL                                                                           0x1633
mmMPCC0_MPCC_CONTROL 6542 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC0_MPCC_CONTROL                                                                           0x1274
mmMPCC0_MPCC_CONTROL 5604 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC0_MPCC_CONTROL                                                                           0x1274