mmMP1_SMN_PUB_CTRL  338 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP1_SMN_PUB_CTRL                                                                             0x02c5
mmMP1_SMN_PUB_CTRL  370 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP1_SMN_PUB_CTRL	0x02c5