mmMP1_SMN_IH_SW_INT_CTRL  330 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
mmMP1_SMN_IH_SW_INT_CTRL  334 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
mmMP1_SMN_IH_SW_INT_CTRL  330 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
mmMP1_SMN_IH_SW_INT_CTRL  344 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP1_SMN_IH_SW_INT_CTRL	0x02c3