mmMP1_SMN_IH_SW_INT  328 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
mmMP1_SMN_IH_SW_INT  332 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
mmMP1_SMN_IH_SW_INT  328 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
mmMP1_SMN_IH_SW_INT  342 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP1_SMN_IH_SW_INT	0x02c2