mmMP1_SMN_C2PMSG_95  308 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP1_SMN_C2PMSG_95                                                                            0x029f
mmMP1_SMN_C2PMSG_95  310 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP1_SMN_C2PMSG_95                                                                            0x029f
mmMP1_SMN_C2PMSG_95  308 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP1_SMN_C2PMSG_95                                                                            0x029f
mmMP1_SMN_C2PMSG_95  320 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP1_SMN_C2PMSG_95	0x029f