mmMP1_SMN_C2PMSG_34_BASE_IDX  187 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
mmMP1_SMN_C2PMSG_34_BASE_IDX  189 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
mmMP1_SMN_C2PMSG_34_BASE_IDX  187 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
mmMP1_SMN_C2PMSG_34_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP1_SMN_C2PMSG_34_BASE_IDX	0