mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX  177 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX  179 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX  177 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX  179 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX	0