mmMP0_SMN_IH_SW_INT_CTRL  176 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
mmMP0_SMN_IH_SW_INT_CTRL  178 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
mmMP0_SMN_IH_SW_INT_CTRL  176 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
mmMP0_SMN_IH_SW_INT_CTRL  178 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h #define mmMP0_SMN_IH_SW_INT_CTRL	0x00c3