mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 1589 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 1229 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 1191 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2