mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX  881 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        0
mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX  881 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        0
mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX  883 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        0
mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1805 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1