mmMC_VM_MARC_BASE_LO_0_BASE_IDX 6597 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                1
mmMC_VM_MARC_BASE_LO_0_BASE_IDX 6843 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                1
mmMC_VM_MARC_BASE_LO_0_BASE_IDX 6867 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                1
mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1799 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                0
mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1831 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                0
mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1815 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX                                                                0