mmMC_SEQ_WR_CTL_D1_LP 1006 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h #define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0
mmMC_SEQ_WR_CTL_D1_LP  819 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h #define mmMC_SEQ_WR_CTL_D1_LP                                                   0xaa0
mmMC_SEQ_WR_CTL_D1_LP  923 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h #define mmMC_SEQ_WR_CTL_D1_LP                                                   0xaa0