mmMC_SEQ_TRAIN_EDC_THRESHOLD  963 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h #define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B
mmMC_SEQ_TRAIN_EDC_THRESHOLD  660 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h #define mmMC_SEQ_TRAIN_EDC_THRESHOLD                                            0xa3b
mmMC_SEQ_TRAIN_EDC_THRESHOLD  764 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h #define mmMC_SEQ_TRAIN_EDC_THRESHOLD                                            0xa3b