mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 1017 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 1601 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 1245 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 1207 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2