mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX  385 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 1549 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 1173 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 1135 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2