mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL  384 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x02d4
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 1548 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 1172 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 1134 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314