mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL  320 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 1484 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 1104 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 1066 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 1573 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5eb8
mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL  775 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5eb8