mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX  309 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 1473 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 1067 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 1029 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2