mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  236 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x0272
mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 1400 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  990 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  952 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 1572 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5e78
mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  774 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5e78