mmMAILBOX_CONTROL_BASE_IDX 1150 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h #define mmMAILBOX_CONTROL_BASE_IDX                                                                     0
mmMAILBOX_CONTROL_BASE_IDX 4501 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h #define mmMAILBOX_CONTROL_BASE_IDX                                                                     2
mmMAILBOX_CONTROL_BASE_IDX 2931 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define mmMAILBOX_CONTROL_BASE_IDX                                                                     2