mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 1855 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 10398 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 12769 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 11343 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2