mmLVTMA_PWRSEQ_REF_DIV 1570 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
mmLVTMA_PWRSEQ_REF_DIV 1395 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
mmLVTMA_PWRSEQ_REF_DIV 1475 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
mmLVTMA_PWRSEQ_REF_DIV 1854 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x209b
mmLVTMA_PWRSEQ_REF_DIV 3953 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmLVTMA_PWRSEQ_REF_DIV 0x191B
mmLVTMA_PWRSEQ_REF_DIV 1283 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmLVTMA_PWRSEQ_REF_DIV                                                  0x191b
mmLVTMA_PWRSEQ_REF_DIV 10397 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
mmLVTMA_PWRSEQ_REF_DIV 12768 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
mmLVTMA_PWRSEQ_REF_DIV 11342 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885