mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 1857 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 10400 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 12771 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 11345 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2