mmGRBM_PWR_CNTL_BASE_IDX 2041 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0
mmGRBM_PWR_CNTL_BASE_IDX   35 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0
mmGRBM_PWR_CNTL_BASE_IDX   35 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0
mmGRBM_PWR_CNTL_BASE_IDX   35 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0