mmGRBM_PWR_CNTL  2040 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGRBM_PWR_CNTL                                                                                0x0da3
mmGRBM_PWR_CNTL    34 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmGRBM_PWR_CNTL                                                                                0x0003
mmGRBM_PWR_CNTL    34 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGRBM_PWR_CNTL                                                                                0x0003
mmGRBM_PWR_CNTL    34 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGRBM_PWR_CNTL                                                                                0x0003
mmGRBM_PWR_CNTL   759 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmGRBM_PWR_CNTL 0x2003
mmGRBM_PWR_CNTL   773 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmGRBM_PWR_CNTL                                                         0x2003
mmGRBM_PWR_CNTL   786 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmGRBM_PWR_CNTL                                                         0x2003
mmGRBM_PWR_CNTL   861 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmGRBM_PWR_CNTL                                                         0x2003
mmGRBM_PWR_CNTL   860 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmGRBM_PWR_CNTL                                                         0x2003