mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 3997 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX                                                               0
mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 1963 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX                                                               0
mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 1907 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX                                                               0