mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 3979 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0
mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1945 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0
mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1889 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0