mmGCEA_DSM_CNTL_BASE_IDX 3009 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGCEA_DSM_CNTL_BASE_IDX                                                                       0
mmGCEA_DSM_CNTL_BASE_IDX 1035 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGCEA_DSM_CNTL_BASE_IDX                                                                       0
mmGCEA_DSM_CNTL_BASE_IDX  999 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGCEA_DSM_CNTL_BASE_IDX                                                                       0