mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 3787 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0
mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1763 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0
mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1705 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0