mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 4999 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 6085 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 5147 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2