mmDSCL3_DSCL_MEM_PWR_STATUS 4998 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x0fd2
mmDSCL3_DSCL_MEM_PWR_STATUS 6084 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x114a
mmDSCL3_DSCL_MEM_PWR_STATUS 5146 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x114a