mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 4524 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 5511 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 4573 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2