mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 3993 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 4881 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 3943 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2