mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 3987 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 4875 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 3937 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2