mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 3989 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 4877 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 3939 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2